Characterization of PVT variation & aging induced hold time margins of flip-flop arrays at NTV in 22nm tri-gate CMOS

With increasing process variation in scaled technology nodes along with voltage and temperature variations and aging degradations, critical timing circuits are impacted which leads to potential loss of performance and yield. In this paper we study the impact of process induced variations on frequency independent min-delay failures in flip-flops in 22nm tri-gate CMOS and demonstrate through novel test-structures the overall impact of within-die and die-to-die hold time fluctuations across a wide range of process skews, temperatures, voltages and aging conditions. This will guide robust silicon-calibrated statistical design methodologies and process targets for min-delay failure mitigation, especially at near-threshold voltage (NTV). Further we demonstrate local clock driver boosting as a potential scheme for yield improvement at NTV, with only 10-20% boost and minimal overheads.