A synchronous wrapper for high-speed heterogeneous systems on FPGAs

Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is interesting for Field-Programmable Gate Array (FPGA) platforms because it facilitates the design of Application Specific Integrated Circuits (ASIC). Through two case studies, the “differential equation solver” and the “FIR Filter”, we show that the proposed synchronous wrapper presents a reduction of up to 27% in the processing time and an increase of up to 747% in the global clock rate when compared with the synchronous design.