PMHLS 2.0: An automated optimization of power management during high-level synthesis

Design automation is very important in modern systems-on-chip development, complexity of which is ever growing. The most crucial issue in highly integrated systems is the increased power density and the corresponding temperature problems influencing reliability. Therefore, the power must be managed in such systems. Power management enables to implement various power-reduction techniques, such as power gating, multiple voltages, or voltage and frequency scaling. However, the automation of power-management design starts at the register-transfer level. Only the recent research begins to adopt power management at the system level of abstraction, which is increasingly used in the industry as a design starting point. In this paper, we propose an enhanced automation of the design process by using the optimized power-management high-level synthesis. This method transforms the system-level power-management specification to the traditionally used form at the register-transfer level. We have implemented this method to a tool called PMHLS, which automates the whole process. It uses optimization decisions to resolve some kinds of inconsistencies and thus makes the power management more efficient. This automation helps to reduce the number of human errors, potentially introduced by a designer during manual design. It also significantly speeds up the system development process. The benefits of the proposed method and the implemented design-automation tool are supported by the experimental results.