A novel fault tolerant voter for identical core in satellite application

As the most quantitative measures of VLSI enactment have enhanced by many orders of level and it has been accomplished by the persistent scaling of the sizes of MOSFETs. However, scaling also impairs fault, noise and reliability issues, thus pretense new challenges in digital circuit design and system. Reliability becomes a foremost concern due to many and often correlated factors, such constraints and/or engineering deviations, aging and soft errors. A Defect and/or fault tolerance may be necessary at several levels throughout the system to improve the reliability of the system. Generally a fault tolerance technique is used to improve the reliability. Quadded logic (QL) is an interwoven redundant logic technique while Quadded Transistor (QT) corrects errors while performing the function of a circuit. The proposed Quadded logic Quadded transistor (QLQT) technique with multi voltage logic to reduce the power consumption and design half adder using this technique. To implement this technique in multiple identical core, TMR is introduced that allows the core to be efficiently tested. A scan chain based technique is employed to recover multiple errors in Triple modular redundancy (TMR) systems. This technique makes use of the scan chain flip-flops that are employed to recover the correct state of a Triple Modular Redundancy system in the presence of temporary or permanent errors. This technique can detect both permanent faults and transient faults. Also a fault tolerant voter identifies multiple faults. The proposed technique improves reliability and reduce the fault. The proposed method is simulated by using Xilinx simulator.