A 0.3–3.3GHz low power, low noise figure, high gain inductor-less wideband CMOS LNA

A wideband CMOS LNA, forehead and most important block in receiver chain is presented in the paper. The proposed architecture incorporates multiple feedback paths to optimize all the performance parameters. Moreover, the architecture is made inductor-less to avoid use of bulky area and power hungry inductors thereby reducing the overall parasitic elements contributed by the use of inductors. The proposed CGLNA architecture simulated using TSMC 90nm CMOS technology covers frequencies from 0.3-3GHz. The results exhibit a maximum gain of 14.7 dB with an upper 3-dB cutoff frequency of 3.3 GHz. Also the minimum NF obtained is 3.23 dB with an IIP3 of -2.9 dBm for frequency of 850 MHz with a 1 MHz spacing. The reflection coefficients are under -10 dB with an isolation below -40 dB.