Concurrent device/circuit aging for general reliability simulations

Continuous shrinking of design window for circuit reliability requires more accurate aging simulation tools. In this paper we describe one concurrent device/circuit aging method for general reliability simulations with improved accuracy. Several circuit reliability mechanisms under modern design concepts are described first, including the negative bias temperature instabilities (NBTI), the self-heating effect on reliability and the electromigration (EM) with design schemes such as dynamic voltage and frequency scaling. The aging simulation methodology currently being used is reviewed, which is inefficient in handling these emerging reliability problems. One possible solution, the dynamic time evolution method (DTEM), is introduced which supports the concurrent device and circuit aging simulations. It is shown that DTEM reproduces the complex reliability behaviors in the transistor level and provides a general framework for isolated or coupled reliability mechanisms in the circuit level.