LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder

As the chip size is getting decreased with the advent of technology, power dissipation has become a major issue to the circuit designers at the time of designing an integrated circuit. The substantial sources of power dissipation are the static power and dynamic power. A serial adder, one of the vital parts of any processor micro-architecture, is a victim to the huge power flow. In this paper, we have intervened on the solution for controlling both static and dynamic power flow by implementing the LECTOR based clock gating technique on the sequential elements of serial adder. LECTOR helps to reduce the static power by blocking the current between the power lines and gated clock minimizes the dynamic power by eliminating the needless switching of system clock. The simulation is carried out using 32nm, 45nm, 65nm and 90nm Predictive Technology Model and compared the result with Double Gated flip-flop based serial adder.