Allocation of multi-bit flip-flops in logic synthesis for power optimization

In this paper, a new approach to the problem of allocating multi-bit flip-flops for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) placing single-bit flip-flops under circuit timing constraints and (ii) minimizing the flip-flop and clock tree power by grouping single-bit flip-flops to form multi-bit flip-flops. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of power consumption. Consequently, we try to minimize power consumption by synthesizing multi-bit flip-flops first and then to place them later. For a number of benchmark circuits, it is shown that our approach of early consideration of synthesizing multi-bit flip-flops is very effective, reducing the clock power by 13.5% while satisfying all the timing constraints.