Modeling Interconnect Variability at Advanced Technology Nodes and Potential Solutions

The advent of multigate transistor technology for 20-nm technology node and beyond, has increased the importance of wire parasitics, in particular, wire resistance in determining the circuit delay computation. Variability in wire dimensions directly impacts the wire parasitics, hence, the overall system performance. For the first time, in this paper, we study circuit variability for 11- and 7-nm technology nodes based on GDSII-level layouts. We propose novel hybrid multipatterning flows, which combine the litho-etch-litho-etch and self-aligned-spacer technologies, to reduce circuit variability induced by the lithography process. We engineer the hybrid solutions to have reduced variability in wire resistance, and circuit performance, and develop variability models for each patterning proposal. We also find the increasing need of these hybrid solutions at the 7-nm technology node. For Extreme Ultraviolet (EUV) lithography to enable higher circuit performance than the proposed patterning regimes, it requires a high precision in core variation of less than 1 nm.