Study of data hazard and control hazard resolution techniques in a simulated five stage pipelined RISC processor

A pipelined RISC architecture can be bifurcated in to five different stages, namely Instruction fetch, Instruction Decode, Execution, Memory and Write back. All of these stages work in a synchronous manner with each other and forward instructions to the next consecutive stage with each passing cycle. Each incoming instruction will first enter the Instruction fetch stage. Then it will be evaluated and carried to the final Write back stage, where its value is updated in the general purpose register set. Problem arises when consecutive instructions in the pipeline have data dependencies and the succeeding instruction does not get the correct value. As the value required by the succeeding instruction is being evaluated in the preceding instruction and is not been updated in the general purpose register set yet. This situation is referred as Data hazard. Further there exist another type of hazard in this type of pipelined architecture known as Control hazard. Control hazard arise due to inability of the processor to decide which instruction to be fetched next within time. In this paper we will study the different techniques to resolve these hazards.