Built in self testing for detection of coupling faults in semiconductor memories

In this work we investigate the problem of detection and location of single and unlinked multiple pattern sensitive faults in bit oriented RAMs and implementation of a built-in self-test (BIST) unit to test RAM chips in an efficient manner. Our fault model covers cross-talks between any k cells in RAMS. We have reduced the problem of memory testing to the problem of the generation of exhaustive back grounds. Exhaustive tests for detecting coupling faults for k up to 6 (which covers Type I neighborhood) and near exhaustive tests for k up to 9 (which covers Type II neighborhood) are constructed. The systematic nature of the tests constructed enables us to use BIST schemes, for RAMs, with low hardware over heads. We implemented the BIST units for a bit-oriented memory of size IM and calculated the hardware overhead in terms of transistors and area.