A 11-Bit Integrating Analog to Digital Converter

This paper describes an integrating analog to digital converter (iADC) based on the dual slope principle. This circuit was designed, fabricated and evaluated in course of a student project in the master degree program ISCD - Integrated Systems and Circuits Design of Carinthia University of Applied Sciences. The mixed-signal circuit consists of the analog front end with integrator and comparator stages, switches as well as current references and a digital control part, fabricated in a 0.35 um CMOS technology. A novel common mode control technique has been implemented for the integrating amplifier and filter caps are added to improve the overall iADC performance. Measurements on fabricated samples show that, with a 997 Hz input, the iADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.94 dB, spurious-free dynamic range (SFDR) of 49.53 dB, effective number of bits (ENOB) of 8 bit, peak integral non-linearity (INL) of 0.6/-5.8 LSB and peak differential nonlinearity (DNL) of 6.5/-1 LSB. The active area of the iADC is 620 μm × 148 μm, and the power dissipation is 19.8 mW from a 3.3 V supply.