Panel: parasitic extraction accuracy; how much is enough?

The effect of parasitic elements on chip performance is well known, however the relative importance of this effect is becoming more critical to a chip's performance. To cope with this new design hazard there are a number of parasitic extraction tools and methodology approaches available to the circuit designer. Some developed for the general market and some developed for internal use. With each product having its own claims and approaches, deciding on a tool or extraction strategy is a confusing exercise. The purpose of this panel is to help the designer and CAD manager determine how to properly compare extractors and how to put them to use. The panel will address a number of questions including; What is the best way to accurately handle parasitic extraction while dealing with increasingly large and complex (SOC, mixed signal) chips? How to determine and achieve the required extraction accuracy for a particular design situation? How is extraction accuracy measured? How can each extractor be compared and contrasted with some degree of confidence? Can circuit design techniques and/or tool methodologies be used to reduce the extraction effort? How should process variations or inductive effects be handled? What's the best way to deal with the data volume problem?