VerTGen: An automatic verilog testbench generator for generic circuits

With the ever growing complexity of hardware designs, their functional verification has become quite a challenge. Despite other techniques like emulation and formal verification methods, simulation continues to be the most common and primary technique to functionally verify the hardware design written in Verilog. Due to the limited computational resources, exhaustive testing of the present-age complex hardware designs is not possible. This makes the selection of vectors very important. However, manual selection of test vectors has often resulted in biased testing and their is always a risk of missing some important corner case. Random testing may solve this problem but manual development of random test generation is a time consuming task. The main contribution of this paper is to facilitate the testbench development task as it presents an automatic random test bench generator tool, VerTGen, for Verilog models. VerTGen has a user friendly GUI and supports all the major probability distributions and can be used to create test benches for both combinational and sequential circuits. For illustration, the paper presents the test bench creation process of a shift register using VerTGen.