Fully pipelined-loop unrolled AES with enhanced key expansion

This paper presents a high throughput, area optimized FPGA based design of the 128-bit Advanced Encryption Standard (AES) algorithm using a combination of techniques such as pipelining, sub-pipelining and loop unrolling. To make a tradeoff between area and throughput, a modified AES architecture is proposed. Multiplication by 2 and 3 in MixColumns operation is redesigned using multiplication by 2 module alone (serial) to reduce the area. To minimize the security issues due to the traditional key expansion algorithm an enhanced key expansion scheme is used. This will shield the design from power analysis and saturation attacks. A pipelined architecture for the same is created.