Programmable FSM based built-in-self-test for memory

In this paper, a design methodology for MBIST (Memory Built In Self Test) which has a feature of executing multiple March algorithms to detect faults is proposed. SOCs have a wide range of memories. It is not possible to test different memory modules of a SOC with a single algorithm. Hence it is desirable to have a programmable MBIST controller capable of executing multiple test algorithms. The proposed MBIST controller is designed as a FSM (Finite State Machine) having less number of states compared to the previous design. The controller is written in Verilog HDL and the experimental results show that the proposed design achieves reduced area and improved speed.