Hybrid digital pulse width modulator architecture using FPGA

This paper deals with hybrid Digital Pulse Width Modulator (DPWM) architecture to generate a variable duty cycle pulse to control the switch of power converters. The proposed architecture highly utilizes the logic blocks present in Field Programmable Array (FPGA) to derive the variable duty cycle Pulse Width Modulation (PWM) pulses. This architecture uses the clock multiplying capability of on chip Digital Clock Manager (DCM) present in FPGA to derive clock frequency doubled of input clock frequency which minimizes the usage higher external clock frequency. The proposed design uses the gray encoding mechanism combined with a decoder to derive a variable duty pulse rather than a binary encoding scheme and a comparator used in traditional DPWM architectures. This approach minimizes the power consumption and best utilizes the logic resources available in FPGA. The design is tested experimentally with low cost SPARTAN 3A and results are shown in Digital storage Oscilloscope.