An on-chip jitter tolerance test circuit for mobile and video interfaces

We proposed an on-chip jitter injection circuit embedded in phase-locked-loop for jitter tolerance test of clock and data recovery circuit. The proposed jitter modulation block consists of divider, signal modulator, and modulating charge pump to inject the sinusoidal voltage to the VCO control voltage. Jitter modulation frequency and amplitude cover the jitter tolerance mask for DisplayPort v1.2 from 1 MHz to 100MHz. The test circuit was implemented using a 28 nm CMOS technology for a 4 Gbps interface.