Optimization of area and power in multi-mode power gating scheme for static memory elements

This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), we can reduce area overhead and leakage power consumption. The simulation results show that the area overhead of SRAM with the proposed approach is reduced from 33.4% to 21.8% compared to that of SRAM with usual MMPG. On the other hand, leakage power is reduced by 12.35% compared to SRAM with usual MMPG and by 86.77% compared to SRAM without power gating scheme. Moreover, the ability of noise immunity of SRAM with proposed approach can also be improved.