Verification of a calibration method for digital to analog converters

A new calibration method for digital to analog converters (DAC) is verified, measuring a set of chips, each containing a 8 bit current steering DAC with a 5+3 segmented architecture. For a sampling frequency of 500MHz and a bandwidth of 5MHz all tested circuits exhibited, after calibration, a Spurious Free Dynamic Range (SFDR) better than 50dB. For a sampling frequency of 1GHz and a bandwidth of 10MHz, a SFDR better than 40dB resulted for all tested cases. These last results could be explained by a degradation of the digital signal supplied by the FPGA board, which has a maximum reliable clock frequency of 600MHz, and by the influence of the parasitic elements introduced by the PCB traces. In all measured cases an improvement of 2-4dB of the SFDR value has been obtained using the proposed calibration method.