A built-in defective level monitor of resistive open defects in 3D ICs with logic gates

Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the changing process of a resistive open defect can be monitored at a test speed of 500 kHz.