All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface

The transmitter driver and the data recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ~ 400 mV swing for normal operation and a 0 ~ 800 mV swing for chirp operation. The data recovery circuit was implemented by using a blind over-sampling method with 5-phase 480 MHz clocks. The proposed transmitter driver and data recovery circuits were fabricated in a 65 nm CMOS process; the transmitter driver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the data recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 data and a USB2.0 5m cable. The transmitter driver and the data recovery circuit consume 24.3 mW and 1.6 mW, respectively at 1.2 V supply.