Critical-Area-Aware Test Pattern Generation and Reordering

Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to accurately estimate defect level, the authors have proposed weighted bridge fault coverage estimation. In this study, we establish unified weighted fault coverage, which takes both bridge and open faults into account, and we propose fast and compact test pattern set generation. The proposed scheme applies two-step test pattern generation where only second pattern set is reordered with search window for speed-up. Compared to simple greedy-based reordering, the experimental results indicate that the proposed scheme with a 10% initial target fault size and a 10% window size achieves approximately 10 times processing time reduction in exchange for a 10% pattern count increment.