Test and Reliability Issues in 2.5D and 3D Integration

Increasing wire delay and higher interconnect power consumption are major concerns for nanoscale CMOS ICs. Three-dimensional integrated circuits (3D ICs) based on through-silicon-vias (TSVs) appear to be a promising solution to overcome bottleneck in CMOS scaling. However, volume production and commercial exploitation of 3D ICs are not feasible before pressing concerns about heat dissipation and test cost, as well as manufacturing yield and resiliency challenges are adequately addressed. At present, interposer-based 2.5D ICs are being advocated as a precursor to 3D ICs. All the dies in a 2.5D or 3D IC must be adequately tested for product qualification. Moreover, the introduction of TSVs for both signal routing across multiple dies as well as power delivery network (PDN), imposes new challenges in terms of manufacturing yield and resiliency issues which should be addressed in both design and test flows. The purpose of this special session, consisting of a set of talks given by experts from the US, Asia and Europe, is to present the test and resiliency challenges faced for the 2.5D and 3D integrated circuits, and discuss the path to overcome such challenges.