Area-efficiency trade-offs in integrated switched-capacitor DC-DC converters

This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated.