Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0–100 pF capacitive load. The design has been implemented in a 0.18 μm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V–1.4 V supply. A current step load from 250–500 μA with an edge time (rise and fall time) of 1 ns results at ΔVOut of 64 mV with a settling time of 3 μs when CL =0. The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.