Charge-Steering Latch Design in 16 nm FinFET Technology for Improved Soft Error Hardness

A charge-steering based latch hardening technique with very low performance tradeoff and significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to illustrate the effect of charge steering in reducing the amount of collected charge at the critical sensitive nodes. Circuit simulations also highlight that the tradeoffs in terms of area, speed and power penalties are much lower compared to other hardening approaches, such as hysteresis and spatial-redundancy techniques. Alpha particle, heavy-ion, and proton test results for circuits designed in a 16 nm FinFET process indicate significant SEU hardness, comparable to DICE FF design, for low LET particles.