A 0.6V standard cell library in 40nm CMOS for near-threshold computing

Processor operating at near-threshold voltage shows improved energy efficiency across many applications. This paper describes a 40nm 0.6V standard cell library used in the implementation of a secure hash algorithm (SHA) accelerator core. An improved cell sizing scheme has been proposed. Validation of single cell show better static noise margin and delay variation under process variation at ultra-low voltage (ULV). Compared with the commercial library, benchmark circuit show improved performance and lower power consumption when synthesized with our library. Utilizing the standard cell library, the SHA accelerator core scales as synthesized from better performance at 1.1V down to lower power at 0.6V.