High-performance VLSI through package-level interconnects

A packaging technique utilizing controlled-collapse chip connection to integrate two existing high-performance VLSI devices into a single pin-grid-array (PGA) package is described. The design and layout of the multilayer ceramic package, electrical and thermal performance, and future enhancements are discussed. The performance of the package is compared to that of a companion two-cavity, wire-bonded evaluation package. The potential use of the packaging technique as a substitute for wafer-level integration is examined.<>