A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library

A high speed 64b/32b integer divider employing digit recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses radix-4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing Compass 0.6 /spl mu/m 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. A real chip is fabricated and fully tested. The test results turn out to be very impressive. A performance evaluation of a 128b/64b signed integer divider using the same design methodology is also included in this study.