A technique for designing self-checking logic for FPGAs

A technique for designing self-checking combinational logic for implementation in look-up table based FPGAs is presented. The technique is based on mapping Boolean functions into FPGAs such that self-checking features are automatically incorporated into designs, allowing on-line detection of faults in the combinational function block within any CLB of an FPGA, and on the interconnect lines that connect these blocks.