A novel DHT-based FFT/IFFT processor for ADSL transceivers

This paper presents a novel discrete Hartley transform based VLSI architecture for quickly computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT), where N is a power of two. The architecture consists of one real multiplier, three real adders, five special memory units, and some simple logic circuits. It can evaluate, in average, one DFT sample every log/sub 2/N+2 clock cycles or one IDFT sample every log/sub 2/N+1 clock cycles. Under 0.6 /spl mu/m CMOS technology, the proposed design consumes chip area about 4838/spl times/4032 /spl mu/m/sup 2/ to reach a throughput of 4 M DFT samples per second or 3.6 M IDFT samples per second for the case of N=512. Such area-time performance shows that it is rather attractive for use in discrete multitone based ADSL transceivers.