An RTL power optimization technique based on System Verilog assertions

This paper presents a novel technique based on System Verilog assertions to optimize the consumed power of RTL designs. The proposed technique helps the designer to enhance his RTL code towards achieving low power design. The designer codes the proposed technique according to the design specifications and integrates the coded technique into his test bench. The coded technique generates directive massages which will be followed to modify and enhance the design code to reduce the consumed power of the design. The idea behind this technique is to monitor the whole design signals. Thus, this technique is a design-dependent technique as it depends on the design specifications. The coded technique determines the targeted signals of the specific input then it displays the mistakenly setting signals which may consume additional wasted power. This technique can be applied and included in any verification framework like the Universal Verification Methodology (UVM) to integrate the power optimization feature of this technique with the features of the used framework. Through applying this technique, the consumed power of the design is significantly reduced as it catches each unused design signal that consumes additional wasted power. This paper explains how to apply the proposed technique with respect to any design specifications and also provides the technique code itself of a simple RTL case study. Moreover, it also attaches the resultant directive massages and presents a comparison between the consumed power before and after the modification of the RTL code according to the directive massages of the coded technique.