Design of fault tolerant digital integrated circuits based on quadded transistor logic

In this paper, we propose a new method based on logic gates including quadded transistors to improve the Soft Error Rate (SER) of combinational circuits. Since the proposed method imposes considerable area overheads, we cannot apply it to all gates of the circuit to improve the circuit SER. So, at first, we identify the gates which are more sensitive to soft errors using a computational model. Then, we propose a method in order to reduce the SER of the circuit. This method optimizes the circuit SER considering the overheads on circuit area. Experimental results based on simulations performed on ISCAS'85 benchmark circuits show that the method can provide an SER reduction of up to 19% with less than 53% area overhead.