Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling

This paper presents high-speed differential CMOS circuits for giga bit per second serial data transmission. The circuits include input and output (I/O) interfaces and a flipflop for retiming. Signal levels are compatible with industry standards for low-voltage positive ECL, with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pull-ups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. The circuits were implemented in a 0.35 /spl mu/m CMOS process and tested at 622 Mb/s and 1.24 Gb/s. The asynchronous performances of the transmitter and the receiver were tested at rates up to 2.5 Gb/s.