The challenge of designing global signals in UDSM CMOS

This paper describes several of the challenges facing designers of global signals in high-performance, ultra-deep submicron (UDSM) CMOS designs. Practical guidelines and a building block approach are presented to solve or avoid problems with global signals as the technology shrinks to 0.25 micron and below. Power distribution is also treated as a global signal. Guidelines are presented for estimation, planning and implementation of global signals. The objective is to present a methodology that will provide a sound foundation for building systems-on-a-chip and resolve methodology and modeling issues early in the design cycle.