Architecture for parallelizing decoding of marker-free variable length code streams

Parallel decoding of encoded data streams is an important scheme that is widely applied in image and video applications. Especially with the increasing demand on higher resolutions and frame rates, parallel decoding becomes very useful to meet the throughput requirements. Parallel decoding is conventionally enabled by inserting markers into the variable length code (VLC) stream. The markers allow for an easy separation of the sub-streams in order to be processed in parallel. The use of markers, however, adversely affects the compression making it unfavorable especially when the bandwidth of the channel is almost fully utilized. In a previous work, we proposed a proof of concept marker-free architecture that enables parallel decoding exhibiting the feasibility of the solution. In this paper, an efficient marker-free architecture is proposed. The memory requirements and the performance of the architecture are thoroughly analyzed. The architecture preserves the original compression factor of the system in contrary to the marker-based approaches. In the experimental results, it is shown that the architecture can be readily configured to drive up to 20 parallel decoders on a medium range FPGA at high clock rates. In addition, the hardware resources in terms of LUTs, registers and block RAMs are reported from which it can be seen that the resources tend to scale linearly with the number of decoders.