A study on construction of Low-Density Parity-Check codes using nonlinear feedback shift registers

Digital communications are daily used in the modern society supported by ICT (Information and Communication Technology). In digital communications, an error-control technology is necessary for correcting/detecting bit errors caused by channel noise. Many kinds of error-correcting/detecting codes have been proposed. Among them, LDPC (Low-Density Parity-Check) codes are known to have error-correcting ability that is near to the Shannon limit. In this paper, we propose the construction of LDPC (Low-Density Parity-Check) codes based on de Bruijn sequences generated by NFSRs (Nonlinear Feedback Shift Registers). The BER (Bit Error Rate) performance of the proposed codes is also evaluated.