Thin MLCC (multi-layer ceramic capacitor) reliability evaluation using an accelerated ramp voltage test

For every semiconductor device, digital processor, FPGA (field programmable gate array), etc. on a typical electronics board, there are usually a dozen or more associated MLCCs. They perform power supply bypassing, DC isolation, EMI filtering functions and many others. Over the last decade in the drive toward higher density, the number of multilayered stacks have increased to the hundreds, while the dielectrics (typically doped BaTiO3) have become thinner, approaching the submicrometer regime. We have developed a technique to evaluate MLCC reliability using a ramp voltage method that can be completed in a week in highly accelerated fashion. We describe the analytical model for MLCC reliability using the effective thickness concept to characterize defects that dominate the early (infant) and midterm (adolescent) reliability. Example ramp data for a typical MLCC and the resulting cumulative defect density and failure rates are shown. The reliability improvement by electrical screening is also evaluated.