Predictive method for simultaneous switching output jitter of DDR for FPGA

Memory system level Simultaneous Switching Output (SSO) timing variation analysis requires a significantly large amount of simulation time and computing resource. Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM) signal integrity analysis requires a complex model that includes numerous data signals, package routing model and Power Delivery Network (PDN) models. Besides, signal analysis and optimization requires multiple simulation iterations. Generally, Field Programmable Gate Array (FPGA) comes in a package matrix where one FPGA device has a few different package types of Input/output (I/O) counts and DDR counts to suit its application. Hence, FPGA needs a long SSO analysis time to cover these package variations. This resulted in a long product cycle time for FPGA. This paper discusses a methodology to build a predictive tool for DDR's SSO noise estimation based on IO mutual inductance (L) coupling and PDN performance calculations of different packages. The test vehicle used was a low cost FPGA with DDR3 600Mbps of x16 DQ in a wirebond package. The correlation between the SSO predictive tool and characterization measurement is also discussed in this paper.