Leveraging Semantic Links for High Efficiency Page-Level FTL Design

NAND Flash Solid State Disks (SSDs) are gainingtremendous popularity in today's storage market due to theirlow energy consumption and high I/O performance. To maskthe unique erase-before-write feature of NAND flash, the FlashTranslation Layer (FTL) in SSD redirects the incoming writesto a free physical address and manages a logical to physicaladdress mapping table. However, the increasing capacity of SSDhas lead to mapping tables large in size, which not only imposehigh pressure on the efficiency of page-level address mapping, but also induces significant performance degradation to SSD. To overcome this problem, Correlation-Aware Page-level FTL(CPFTL) is proposed in this work. CPFTL uniquely leveragesthe inherent data semantics in enterprise workloads to optimizemapping table cache management. First, a correlation-awaremapping table is developed based on the correlation in readoperations. We then propose a correlation prediction table tosupport fast mapping entry lookup in correlation-aware mappingtable. Our experimental results show that CPFTL reduces theaverage response time by 63.4% for read dominant workloadsand 32.9% for transaction workloads.