Low power design of asynchronous SAR ADC

In this paper 8 bit SAR ADC with input voltage of 1.2V has been designed. The schematic diagram of different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. Comparator was designed so that it remains in saturation for proper operation and was implemented using differential amplifier. The comparator is the main power consuming block, so most of our effort was focused on designing this block. In order to increase the precision, the R-2R ladder network was used for implementing DAC sub block. For driving ADC, asynchronous control logic was designed using Verilog coding, so there was no need for using a clock.