Design and implementation of quaternary summation circuit with single electron transistor and MOSFET

This paper presents a novel approach for designing of quaternary logic SETMOS summation circuit, hybrid circuits consisting of SET & MOSFET. Various gates based on hybrid structure also presented & simulated. The simulated outcomes shows that these hybrid circuits appreciates some parameters such as power dissipation and speed as compared with pure SET or pure CMOS circuits. These logic gates are used for further design of summation circuit for quaternary logic.