Development of 7-level cascaded H-bridge inverter topology for PV applications

One of the basic problems in power conversion is the harmonic content at output level. Generally harmonics can be categorized as current and voltage harmonics. Harmonics can be minimized either by increasing the number of voltage levels or by using appropriate modulation techniques. In this paper both mechanisms are proposed. The proposed inverter is 7-level Cascaded Multilevel Inverter (CMLI). As per the simulation results number of output voltage levels increases harmonics will be reduced. And also different Pulse Width Modulation techniques are employed. Among these modulation techniques, selective harmonic elimination technique has fewer harmonic for same number of output voltage levels. The simulation work developed by using MATLAB-Simulink® software of version 13.3a. Comparison on different PWM carrier based and selective harmonic elimination method are also presented.