Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application

This paper represents the energy efficient ultra low power adiabatic sequential logic circuits in sub-threshold regime for the first time in literature. Here, Efficient Charge Recovery Logic (ECRL) based on Differential Cascode Voltage Swing (DCVS) is adopted for the implementation of the circuits to achieve the ultra low power dissipation in sub-threshold regime. Single sinusoidal source is used as supply clock to enjoy the minimal power overheads. In this paper, adiabatic flip-flops and 8 bit Parallel — In — Serial — Out (PISO) shift register have been implemented in sub-threshold regime. Extensive CADENCE simulations for the first time in 22 nm technology node ensure that in sub-threshold regime, ECRL based flip-flops consume only 35% to 45% of total energy consumed by the static CMOS counterpart.