High performance redundant binary multiplier

High speed multiplier designs have been the primacy for multiplier dominated applications such as wireless communications, computer applications, and image processing. In this paper a high performance fixed word length multiplier design by using recently proposed technique to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary (RB-NB) conversion has been proposed. These techniques are selected to make achievable tradeoff for area, power and delay. Due to carry-free addition and adaptability, the redundant binary (RB) representation has been picked up in our high-performance multiplier design for partial product summing tree. This multiplier architecture is compared with the design of conventional redundant binary modified booth encoding multiplier (CRBMBE) for area, power and delay analysis. The designed architecture shows improved performance over conventional redundant binary multiplier in terms of area, delay and power-delay product (PDP).