Implementation of three operand floating point adder

In this paper, a three operand floating point adder with reduced delay has been implemented. In this, the internal width which mainly gives the delay has been given compatible with IEEE Std-754. Here for designing three operand floating point adder, Realignment method, which avoid more than one sticky generation, an low cost OR-logic network in the replacement of comparer has been employed, to detect catastrophic cancellation. For implementing three operand floating point adder, Carry save Adder (CSA) is used rather than Ripple Carry adder (RCA) as CSA requires less time to process the input as compared to RCA. To optimize the architecture of complete design, leading zero anticipator (LZA) and compound adder are used. In the proposed design the delay is reduced by 7.79% as compared with the referred three operand adder.