Design and implementation of 64 bit multiplier using vedic algorithm

As floating point architecture is very hot topic for researchers so challenges are always there to design the efficient Floating point architecture. Out of other operations, Floating point multiplication is the most commonly used operation and it requires the multiplication of the mantissa of Floating point numbers. This paper presents the highly efficient 64 bit multiplier for the mantissa calculation using rule or sutra of Vedic mathematics called Urdhva Tiryakbhyam Sutra which deals with vertically and crosswise multiplication. Using this sutra in the computation algorithm of DSP processors, can enhance the efficiency and at the same time can reduce the complexity, area, power consumption and delay. Starting from the design of 2 bit Vedic multiplier we went up to design 64 bit Vedic multiplier as presented in this paper. Vedic multiplier is coded in Verilog HDL and targeted to three different families of FPGA Spartan6, Virtex5 and Virtex6 in Xilinx 13.1 ISE software. Result is compared with the Karatsuba, Vedic-Karatsuba and Optimized Vedic multiplier and found 33% reduction in delay.