Optimistic clock adjustment for preventing Better-than-worst-case violations

This paper proposes a technique for reducing power consumption and increasing pipeline performance using the state of art “Better than worst case” design. This method uses a violation predication mechanism that places the optimum number of Transition Detectors and a novel Time Borrowing technique to prevent potential timing errors. In this work the tradeoff between power consumption (Transition Detectors dynamic and leakage power) and accuracy of prediction is examined and the optimum number of transistors is placed on the circuit based on the available power budget.