PLL control voltage stabilization method for high-speed systems

High-speed PLL control voltage stabilization method is presented in the paper. Fully integrated modified PLL circuit is designed accordingly. Stabilization principle is based on compensation of the LPF MOSFET capacitor output voltage which is unstable due to gate oxide leakage currents. Stabilization is implemented by using analog latch circuit and holding correct VCO control voltage. Latched voltage can be refreshed by digital logic block when PVT variation is detected in the system. The presented compensation method can be used in the I/O circuits of such standards as DDR (Double Data Rate), USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), etc.